Method for forming silicon/germanium containing drain/source regions in transistors with reduced silicon/germanium loss

US8652913B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Andreas Gehring · Dresden, DE
• Maciej Wiatr · Dresden, DE
• Andy Wei · Queensbury, US
• Thorsten Kammler · Radeberg, DE
• Roman Boschke · Dresden, DE
• Casey Scott · Dresden, DE

Key dates

• Filing date: Jul 17, 2007
• Grant date: Feb 18, 2014
• Expiry date: Jan 29, 2031

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D62/822

Abstract

By providing a protection layer on a silicon/germanium material of high germanium concentration, a corresponding loss of strained semiconductor material may be significantly reduced or even completely avoided. The protection layer may be formed prior to critical cleaning processes and may be maintained until the formation of metal silicide regions. Hence, high performance gain of P-type transistors may be accomplished without requiring massive overfill during the selective epitaxial growth process.