Enhanced transistor performance of N-channel transistors by using an additional layer above a dual stress liner in a semiconductor device

US8697584B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Ralf Richter · Dresden, DE
• Andy Wei · Queensbury, US
• Roman Boschke · Dresden, DE

Key dates

• Filing date: Jan 21, 2008
• Grant date: Apr 15, 2014
• Expiry date: Jan 11, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0167

Abstract

By forming an additional dielectric material, such as silicon nitride, after patterning dielectric liners of different intrinsic stress, a significant increase of performance of N-channel transistors may be obtained while substantially not contributing to a performance loss of the P-channel transistor.