Low capacitance transient voltage suppressor (TVS) with reduced clamping voltage
US8698196B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jun 28, 2011 |
| Grant date | Apr 15, 2014 |
| Priority date | — |
| Expiry date | Jan 22, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D89/611
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A low capacitance transient voltage suppressor with reduced clamping voltage includes an n+ type substrate, a first epitaxial layer on the substrate, a buried layer formed within the first epitaxial layer, a second epitaxial layer on the first epitaxial layer, and an implant layer formed within the first epitaxial layer below the buried layer. The implant layer extends beyond the buried layer. A first trench is at an edge of the buried layer and an edge of the implant layer. A second trench is at another edge of the buried layer and extends into the implant layer. A third trench is at another edge of the implant layer. Each trench is lined with a dielectric layer. A set of source regions is formed within a top surface of the second epitaxial layer. The trenches and source regions alternate. A pair of implant regions is formed in the second epitaxial layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.