Thermal management of stacked semiconductor chips with electrically non-functional interconnects
US8704353B2 · kind B2 · utility
4Cited by
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24Claims
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Key dates
| Filing date | Mar 30, 2012 |
| Grant date | Apr 22, 2014 |
| Priority date | — |
| Expiry date | May 9, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of manufacturing is provided that includes fabricating a first plurality of electrically functional interconnects on a front side of a first semiconductor chip and fabricating a first plurality of electrically non-functional interconnects on a back side of the first semiconductor chip. Additional chips may be stacked on the first semiconductor chip.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.