Capacitor top plate over source/drain to form a 1T memory device
US8716081B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Mar 15, 2007 |
| Grant date | May 6, 2014 |
| Priority date | — |
| Expiry date | Mar 28, 2031 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B10/00
Abstract
A method and structure for a memory device, such as a 1T-SRAM, having a capacitor top plate directly over a doped bottom plate region. An example device comprises the following. An isolation film formed as to surround an active area on a substrate. A gate dielectric and gate electrode formed over a portion of the active area. A source element and a drain element in the substrate adjacent to the gate electrode. The drain element is comprised of a drain region and a bottom plate region. The drain region is between the bottom plate region and the gate structure. A capacitor dielectric and a capacitor top plate are over at least portions of the bottom plate region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.