Methods for fabricating integrated circuits having gate to active and gate to gate interconnects

US8722500B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Thilo Scheiper · Dresden, DE
• Stefan Flachowsky · Dresden, DE
• Andy Wei · Queensbury, US

Key dates

• Filing date: Sep 20, 2011
• Grant date: May 13, 2014
• Expiry date: Jul 16, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L21/76897
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

Methods are provided for fabricating an integrated circuit that includes gate to active contacts. One method includes processing the IC in a replacement gate technology including forming dummy gates, sidewall spacers on the dummy gates, and metal silicide contacts to active areas. A fill layer is deposited and planarized to expose the dummy gates and the dummy gates are removed. A mask is formed having an opening overlying a portion of the channel region from which the dummy gate was removed and a portion of an adjacent metal silicide contact. The fill layer and a portion of the sidewall spacers exposed through the mask opening are etched to expose a portion of the adjacent metal silicide contact. A gate electrode material is deposited overlying the channel region and exposed metal silicide contact and is planarized to form a gate electrode and a gate-to-metal silicide contact interconnect.