Two-dimensional shielded gate transistor device and method of manufacture
US8759908B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Nov 1, 2011 |
| Grant date | Jun 24, 2014 |
| Priority date | — |
| Expiry date | Apr 27, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/519
Abstract
A shielded gate transistor device may include one or more shield electrodes formed in a semiconductor substrate at a first level and one or more gate electrodes formed in the semiconductor substrate at a second level that is different from the first level. One or more portions of the one or more gate electrodes overlap one or more portions of the one or more shield electrodes. At least a portion of the gate electrodes is oriented non-parallel to the one or more shield electrodes. The shield electrodes are electrically insulated from the semiconductor substrate and the one or more gate electrodes are electrically insulated from the substrate and shield electrodes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.