Memory cell system with multiple nitride layers
US8809936B2 · kind B2 · utility
0Cited by
9References
18Claims
0Family size
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Key dates
| Filing date | Jul 31, 2006 |
| Grant date | Aug 19, 2014 |
| Priority date | — |
| Expiry date | May 17, 2027 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/685
Abstract
A memory cell system is provided including forming a first insulator layer over a semiconductor substrate, forming a charge trap layer over the first insulator layer, forming a second insulator layer over the charge trap layer, forming a top blocking intermediate layer over the second insulator layer, and forming a contact layer over the top blocking intermediate layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.