Method of adjusting the threshold voltage of a transistor by a buried trapping layer

US8809964B2 · kind B2 · utility

Assignee

• COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES · FR

Inventors

• Francois Andrieu · Meylan, FR
• Emmanuel Augendre · Montbonnot-Saint-Martin, FR
• Laurent Clavelier · Grenoble, FR
• Marek Kostrzewa · Grenoble, FR

Key dates

• Filing date: Feb 11, 2009
• Grant date: Aug 19, 2014
• Expiry date: Dec 16, 2029

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D86/201

Abstract

An electronic subassembly and associated method for the production of an electronic subassembly include a semiconductor layer bearing at least a first transistor having an adjustable threshold voltage is joined to an insulator layer and in which a first trapping zone is formed at a predetermined first depth. The first trapping zone extends at least beneath a channel of the first transistor and includes traps of greater density than the density of traps outside the first trapping zone, in such a way that the semiconductor layer and the first trapping zone are capacitively coupled. The useful information from the first transistor includes the charge transport within this transistor. A second trapping zone can be formed that extends at least beneath a channel of a second transistor that is formed by a second implantation with an energy and/or a dose and/or atoms that differ from those used to form the first trapping zone.