Method for forming gate, source, and drain contacts on a MOS transistor
US8822332B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Apr 26, 2013 |
| Grant date | Sep 2, 2014 |
| Priority date | — |
| Expiry date | Apr 26, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/01
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for forming gate, source, and drain contacts on a MOS transistor having an insulated gate including polysilicon covered with a metal gate silicide, this gate being surrounded with at least one spacer made of a first insulating material, the method including the steps of a) covering the structure with a second insulating material and leveling the second insulating material to reach the gate silicide; b) oxidizing the gate so that the gate silicide buries and covers the a silicon oxide; c) selectively removing the second insulating material; and d) covering the structure with a first conductive material and leveling the first conductive material all the way to a lower level at the top of the spacer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.