Fabrication of semiconductor stacks with ruthenium-based materials
US8828821B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Sep 18, 2009 |
| Grant date | Sep 9, 2014 |
| Priority date | — |
| Expiry date | Feb 21, 2030 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D1/696
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
This disclosure provides a method of fabricating a semiconductor stack and associated device such as a capacitor and DRAM cell. In particular, a bottom electrode upon which a dielectric layer is to be grown may have a ruthenium-based surface. Lattice matching of the ruthenium surface with the dielectric layer (e.g., titanium oxide, strontium titanate or barium strontium titanate) helps promote the growth of rutile-phase titanium oxide, thereby leading to higher dielectric constant and lower effective oxide thickness. The ruthenium-based material also provides a high work function material, leading to lower leakage. To mitigate nucleation delay associated with the use of ruthenium, an adherence or glue layer based in titanium may be employed. A pretreatment process may be further employed so as to increase effective capacitor plate area, and thus promote even further improvements in dielectric constant and effective oxide thickness (“EOT”).
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.