Patent · US Active

Uniform finFET gate height

US8829617B2 · kind B2 · utility

8Cited by

6References

6Claims

0Family size

Assignee

International Business Machines Corporation · US

Inventors

Balasubramanian S. Haran · Watervliet, US
Sanjay C. Mehta · Niskayuna, US
Shom Ponoth · Irvine, US
Ravikumar Ramachandran · Beacon, US
Stefan Schmitz · Stuttgart, DE
Theodorus E. Standaert · Clifton Park, US

Key dates

Filing date	Nov 30, 2012
Grant date	Sep 9, 2014
Priority date	—
Expiry date	Nov 30, 2032

Classification

Technology area (CPC H)Electricity
CPC primaryH10D86/215
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

A method including providing a plurality of fins etched from a semiconductor substrate and covered by an oxide layer and a nitride layer, the oxide layer being located between the plurality of fins and the nitride layer, removing a portion of the plurality of fins to form an opening, and forming a dielectric spacer on a sidewall of the opening. The method may also include filling the opening with a fill material, wherein a top surface of the fill material is substantially flush with a top surface of the nitride layer, removing the nitride layer to form a gap between the plurality of fins and the fill material, wherein the fill material has re-entrant geometry extending over the gap, and removing the re-entrant geometry and causing the gap between the plurality of fins and the fill material to widen.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.