Self-aligned double patterning via enclosure design
US8839168B2 · kind B2 · utility
10Cited by
6References
20Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jan 22, 2013 |
| Grant date | Sep 16, 2014 |
| Priority date | — |
| Expiry date | Jan 22, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG03F1/70
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A design methodology for determining a via enclosure rule for use with a self-aligned double pattern (SADP) technique is disclosed. The shape of the block mask serves as a criterion for choosing a via enclosure rule. Different block mask shapes within an integrated circuit design may utilize different rules and provide different margins for via enclosure. A tight via enclosure design rule reduces the margin of a line beyond the via where possible, while a loose via enclosure design rule increases the margin of a line beyond the via where it is beneficial to do so.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.