Chip package and a method for manufacturing a chip package

US8841768B2 · kind B2 · utility

Assignee

• Infineon Technologies AG · DE

Inventors

• Carsten von Koblinski · Velden am Wörther See, AT
• Michael Knabl · Sattendorf, AT
• Ursula Meyer · Villach, AT
• Francisco Javier Santos Rodriguez · Villach, AT
• Alexander Breymesser · Villach, AT
• Andre Brockmeier · Villach, AT

Key dates

• Filing date: Jul 23, 2012
• Grant date: Sep 23, 2014
• Expiry date: Mar 22, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L2924/351
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A chip package is provided, the chip package including: first encapsulation structure; first passivation layer formed over first encapsulation structure and first electrically conductive layer formed over first passivation layer; at least one chip arranged over first electrically conductive layer and passivation layer wherein at least one chip contact pad contacts first electrically conductive layer; at least one cavity formed in first encapsulation structure, wherein at least one cavity exposes a portion of first passivation layer covering at least one chip contact pad; second encapsulation structure disposed over first encapsulation structure and covering at least one cavity, wherein a chamber region over at least one chip contact pad is defined by at least one cavity and second encapsulation structure; wherein second encapsulation structure includes an inlet and outlet connected to chamber region, wherein inlet and outlet control an inflow and outflow of heat dissipating material to and from chamber region.