Non-volatile memory and method with improved data scrambling
US8843693B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | May 17, 2011 |
| Grant date | Sep 23, 2014 |
| Priority date | — |
| Expiry date | Jul 28, 2032 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F12/1408
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A memory device cooperating with a memory controller scrambles each unit of data using a selected scrambling key before storing it in an array of nonvolatile memory cells. This helps to reduce program disturbs, user read disturbs, and floating gate to floating gate coupling that result from repeated and long term storage of specific data patterns. For a given page of data having a logical address and for storing at a physical address, the key is selected from a finite sequence thereof as a function of both the logical address and the physical address. In a block management scheme the memory array is organized into erase blocks, the physical address is the relative page number in each block. When logical address are grouped into logical groups and manipulated as a group and each group is storable into a sub-block, the physical address is the relative page number in the sub-block.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.