Capacitor designs for integrated circuits utilizing self-aligned double patterning (SADP)
US8856715B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 23, 2013 |
| Grant date | Oct 7, 2014 |
| Priority date | — |
| Expiry date | Jul 23, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/394
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Methodologies enabling BEoL VNCAPs in ICs and resulting devices are disclosed. Embodiments include: providing a plurality of mandrel recesses extending horizontally on a substrate, each of the mandrel recesses having an identical width and being separated from another one of the mandrel recesses by an identical distance; providing a plurality of routes, each of the plurality of routes being positioned in a different one of the mandrel recesses; and providing first and second vertical segments on the substrate, the first vertical segment being connected to a set of the plurality of routes and separated from the second vertical segment, and the second vertical segment being separated from the set of routes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.