Semiconductor arrangement with active drift zone
US8866253B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jan 31, 2012 |
| Grant date | Oct 21, 2014 |
| Priority date | — |
| Expiry date | Jul 27, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/215
- WIPO fieldBasic communication processes
- WIPO sectorElectrical engineering
Abstract
A semiconductor device arrangement includes a first semiconductor device having a load path and a plurality of second semiconductor devices, each having a load path between a first and a second load terminal and a control terminal. The second semiconductor devices have their load paths connected in series and connected in series to the load path of the first semiconductor device. Each of the second semiconductor devices has its control terminal connected to the load terminal of one of the other second semiconductor devices, and one of the second semiconductor devices has its control terminal connected to one of the load terminals of the first semiconductor device. Each of the second semiconductor devices has at least one device characteristic. At least one device characteristic of at least one of the second semiconductor devices is different from the corresponding device characteristic of others of the second semiconductor devices.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.