Methods of reducing material loss in isolation structures by introducing inert atoms into oxide hard mask layer used in growing channel semiconductor material

US8871586B2 · kind B2 · utility

Assignee

• GlobalFoundries Inc. · KY

Inventors

• Thilo Scheiper · Dresden, DE
• Jan Hoentschel · Dresden, DE
• Markus Lenski · Dresden, DE
• Rolf Stephan · Dresden, DE

Key dates

• Filing date: Oct 18, 2012
• Grant date: Oct 28, 2014
• Expiry date: Oct 18, 2032

Classification

• Technology area (CPC Y): Emerging Cross-Sectional Technologies
• CPC primary: Y02P80/30
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

In one example, the method includes forming a plurality of isolation structures in a semiconducting substrate that define first and second active regions where first and second transistor devices, respectively, will be formed, forming a hard mask layer on a surface of the substrate above the first and second active regions, wherein the hard mask layer comprises at least one of carbon, fluorine, xenon or germanium ions, performing a first etching process to remove a portion of the hard mask layer and expose a surface of one of the first and second active regions, after performing the first etching process, forming a channel semiconductor material on the surface of the active region that was exposed by the first etching process, and after forming the channel semiconductor material, performing a second etching process to remove remaining portions of the hard mask layer that were not removed during the first etching process.