Method for manufacturing a hybrid SOI/bulk semiconductor wafer

US8877600B2 · kind B2 · utility

Assignees

• STMICROELECTRONICS, INC. · US
• STMicroelectronics SA
• STMicroelectronics (Crolles 2) SAS · FR
• COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES · FR

Inventors

• Claire Fenouillet-Beranger · Grenoble, FR
• Stephane Denorme · Crolles, FR
• Nicolas Loubet · Guilderland, US
• Qing Liu · Guilderland, US
• Emmanuel Richard · Chambéry, FR
• Pierre Perreau · Grenoble, FR

Key dates

• Filing date: Dec 12, 2013
• Grant date: Nov 4, 2014
• Expiry date: Dec 12, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D87/00
• WIPO field: Semiconductors
• WIPO sector: Electrical engineering

Abstract

A method for manufacturing a hybrid SOI/bulk substrate, including the steps of starting from an SOI wafer comprising a single-crystal semiconductor layer called SOI layer, on an insulating layer, on a single-crystal semiconductor substrate; depositing on the SOI layer at least one masking layer and forming openings crossing the masking layer, the SOI layer, and the insulating layer, to reach the substrate; growing by a repeated alternation of selective epitaxy and partial etching steps a semiconductor material; and etching insulating trenches surrounding said openings filled with semiconductor material, while encroaching inwards over the periphery of the openings.