Magnetoresistive logic cell and method of use
US8885395B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 22, 2012 |
| Grant date | Nov 11, 2014 |
| Priority date | — |
| Expiry date | Jan 18, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10N50/10
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A magnetoresistive logic cell (MRLC) is described that includes two MTJs in series that share a common free layer (CFL). The relative magnetization orientations of the CFL and the switchable reference layer (SRL) in MTJ-1 dominate the overall resistance of the MRLC without regard to the fixed magnetization orientation of the nonswitchable reference layer in MTJ-2. The high resistance state of the MRLC occurs when the switchable reference and common free layers have opposite magnetization orientations. The low resistance state occurs when the orientations are the same. This behavior allows the MRLC to be used as a logical comparator. The CFL is switched by STT effect by application of selected relatively short voltage pulses that do not switch the SRL. The SRL is switched with reference to the CFL by a voltage effect generated by a selected longer voltage pulse that does not switch the CFL.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.