Patent · US Active

Gate-all-around nanowire MOSFET and method of formation

US8900951B1 · kind B1 · utility

32Cited by
4References
15Claims
0Family size

Assignee

Inventors

Key dates

Filing dateSep 24, 2013
Grant dateDec 2, 2014
Priority date
Expiry dateSep 24, 2033

Classification

  • Technology area (CPC H)Electricity
  • CPC primaryH10D62/151

Abstract

A method for fabricating a semiconductor device comprises forming a nanowire on an insulator layer at a surface of a substrate; forming a dummy gate over a portion of the nanowire and a portion of the insulator layer; forming recesses in the insulator layer on opposing sides of the dummy gate; forming spacers on opposing sides of the dummy gate; forming source regions and drain regions in the recesses in the insulator layer on opposing sides of the dummy gate; depositing an interlayer dielectric on the source regions and the drain regions; removing the dummy gate to form a trench; removing the insulator layer under the nanowire such that a width of the trench underneath the nanowire is equal to or less than a distance between the spacers; and forming a replacement gate in the trench.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.