Memory cells

US8921821B2 · kind B2 · utility

Assignee

• Micron Technology, Inc. · US

Inventors

• Shuichiro Yasuda · Boise, US
• Noel Rocklein · Boise, US
• Scott E. Sills · Boise, US
• D. V. Nirmal Ramaswamy · Boise, US
• Qian Tao · Singapore, SG

Key dates

• Filing date: Jan 10, 2013
• Grant date: Dec 30, 2014
• Expiry date: Jan 10, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10N70/8836

Abstract

Some embodiments include a method of forming a memory cell. A first portion of a switching region is formed over a first electrode. A second portion of the switching region is formed over the first portion using atomic layer deposition. The second portion is a different composition than the first portion. An ion source region is formed over the switching region. A second electrode is formed over the ion source region. Some embodiments include a memory cell having a switching region between a pair of electrodes. The switching region is configured to be reversibly transitioned between a low resistive state and a high resistive state. The switching region includes two or more discrete portions, with one of the portions not having a non-oxygen component in common with any composition directly against it in the high resistive state.