Three dimensional NAND device with silicide containing floating gates
US8928061B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 26, 2014 |
| Grant date | Jan 6, 2015 |
| Priority date | — |
| Expiry date | Feb 26, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/665
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A monolithic three dimensional NAND string includes a semiconductor channel located over a substrate, a plurality of control gates extending substantially parallel to the major surface of the substrate including a first control gate located in a first device level and a second control gate located in a second device level located over the substrate and below the first device level, a charge storage material including a silicide layer located in the first device level and in the second device level, a blocking dielectric located between the charge storage material and the plurality of control gates, and a tunnel dielectric located between the charge storage material and the semiconductor channel. The tunnel dielectric has a straight sidewall, portions of the blocking dielectric have a clam shape, and each of the plurality of control gates is located at least partially in an opening in the clam-shaped portion of the blocking dielectric.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.