Three-dimensional NAND memory with adaptive erase
US8929141B1 · kind B1 · utility
2Cited by
21References
19Claims
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Key dates
| Filing date | Oct 2, 2013 |
| Grant date | Jan 6, 2015 |
| Priority date | — |
| Expiry date | Oct 2, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG11C16/3445
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
Erasing memory cells in certain 3-D NAND charge-storage memory arrays is achieved by rapidly charging vertical conductors using Gate Induced Drain Leakage (GIDL) current generated in select transistors. When bit line voltage drops below its nominal value, select line voltage is controlled to maintain a constant voltage difference between bit line voltage and select line voltage thus maintaining a gate-drain voltage difference in select transistors that provides sufficient GIDL current for erase.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.