Contact formation for ultra-scaled devices
US8937359B2 · kind B2 · utility
11Cited by
3References
20Claims
0Family size
Assignees
Inventors
Key dates
| Filing date | May 15, 2013 |
| Grant date | Jan 20, 2015 |
| Priority date | — |
| Expiry date | Jul 5, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76883
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the invention provide approaches for forming gate and source/drain (S/D) contacts. Specifically, the semiconductor device includes a gate transistor formed over a substrate, a S/D contact formed over a trench-silicide (TS) layer and positioned adjacent the gate transistor, and a gate contact formed over the gate transistor, wherein at least a portion of the gate contact is aligned over the TS layer. This structure enables contact with the TS layer, thereby decreasing the distance between the gate contact and the source/drain, which is desirable for ultra-area-scaling.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.