Integrating optimal planar and three-dimensional semiconductor design layouts
US8966423B2 · kind B2 · utility
5Cited by
2References
12Claims
0Family size
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Key dates
| Filing date | Mar 11, 2013 |
| Grant date | Feb 24, 2015 |
| Priority date | — |
| Expiry date | Mar 11, 2033 |
Classification
- Technology area (CPC G)Physics
- CPC primaryG06F30/392
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
An approach and apparatus are provided for optimizing and combining different semiconductor technologies into a single graphic data system. Embodiments include generating a planar semiconductor layout design, generating a three-dimensional (e.g., FinFET) semiconductor layout design, and combining the planar design and the FinFET design in a common graphic data system.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.