Patent · US Active

Semiconductor device arrangement with a first semiconductor device and with a plurality of second semiconductor devices

US8970262B2 · kind B2 · utility

27Cited by

17References

25Claims

0Family size

Assignee

Infineon Technologies Austria AG · AT

Inventors

Rolf Weis · Dresden, DE
Franz Hirler · Isen, DE
Martin Feldtkeller · Munich, DE
Gerald Deboy · Klagenfurt, AT
Matthias Stecher · Munich, DE
Armin Willmeroth · Friedberg, DE

Key dates

Filing date	Jan 9, 2012
Grant date	Mar 3, 2015
Priority date	—
Expiry date	Jan 9, 2032

Classification

Technology area (CPC H)Electricity
CPC primaryH10D84/87
WIPO fieldBasic communication processes
WIPO sectorElectrical engineering

Abstract

Disclosed is a semiconductor device arrangement including a first semiconductor device having a load path, and a plurality of second transistors, each having a load path between a first and a second load terminal and a control terminal. The second transistors have their load paths connected in series and connected in series to the load path of the first transistor, each of the second transistors has its control terminal connected to the load terminal of one of the other second transistors, and one of the second transistors has its control terminal connected to one of the load terminals of the first semiconductor device.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.