Wafer level chip scale package and process of manufacture
US8981464B2 · kind B2 · utility
4Cited by
10References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | May 6, 2014 |
| Grant date | Mar 17, 2015 |
| Priority date | — |
| Expiry date | May 6, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/30107
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Power wafer level chip scale package (CSP) and process of manufacture are enclosed. The power wafer level chip scale package includes all source, gate and drain electrodes located on one side of the device, which is convenient for mounting to a printed circuit board (PCB) with solder paste.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.