Fin isolation in multi-gate field effect transistors
US8987790B2 · kind B2 · utility
19Cited by
5References
15Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Nov 26, 2012 |
| Grant date | Mar 24, 2015 |
| Priority date | — |
| Expiry date | Nov 26, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D86/215
Abstract
A method for fabricating a field effect transistor (FET) device includes forming a plurality of semiconductor fins on a substrate, removing a semiconductor fin of the plurality of semiconductor fins from a portion of the substrate, forming an isolation fin that includes a dielectric material on the substrate on the portion of the substrate, and forming a gate stack over the plurality of semiconductor fins and the isolation fin.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.