Field effect transistor with offset counter-electrode contact
US8994142B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 4, 2012 |
| Grant date | Mar 31, 2015 |
| Priority date | — |
| Expiry date | May 8, 2032 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/76283
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The field effect transistor comprises a substrate successively comprising an electrically conducting support substrate, an electrically insulating layer and a semiconductor material layer. The counter-electrode is formed in a first portion of the support substrate facing the semi-conductor material layer. The insulating pattern surrounds the semi-conductor material layer to delineate a first active area and it penetrates partially into the support layer to delineate the first portion. An electrically conducting contact passes through the insulating pattern from a first lateral surface in contact with the counter-electrode through to a second surface. The contact is electrically connected to the counter-electrode.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.