Defect image processing apparatus, defect image processing method, semiconductor defect classifying apparatus, and semiconductor defect classifying method

US8995748B2 · kind B2 · utility

Assignee

• Hitachi High-Technologies Corporation · JP

Inventors

• Tsunehiro Sakai · Tokyo, JP
• Shigeki Kurihara · Yokohama, JP
• Yutaka Tandai · Tokyo, JP
• Tamao Ishikawa · Hitachinaka, JP
• Yuichi Hamamura · Tokyo, JP
• Tomohiro Funakoshi · Tokyo, JP
• Seiji Isogai · Hitachinaka, JP
• Katsuhiko Ichinose · Tokyo, JP

Key dates

• Filing date: Jun 1, 2010
• Grant date: Mar 31, 2015
• Expiry date: Mar 10, 2032

Classification

• Technology area (CPC H): Electricity
• CPC primary: H01L22/12
• WIPO field: Measurement
• WIPO sector: Instruments

Abstract

A defect image processing apparatus uses a normalized cross correlation to image-match a layout image (52) acquired from a design data with an image acquired by removing, from a defect image (53), the defect area portions thereof, and displays, as a result of that matching, a layout image and defect image (54) on the display device. In the displayed layout image & defect image (54), not only the layout image, the layer of which is the same as that of the defect image (53), but also a layout image of another layer is displayed superimposed on the defect image (53). This makes it easier to analyze the factor of a systematic defect having occurred due to a positional relationship with another layer.