Patent · US Active

Chip arrangement and a method of manufacturing a chip arrangement

US9041226B2 · kind B2 · utility

0Cited by

6References

20Claims

0Family size

Assignee

Infineon Technologies AG · DE

Inventors

Rainer Steiner · Regensburg, DE
Edward Fuergut · Nuremberg, DE
Khalil Hosseini · Weihmichl, DE
Georg Meyer-Berg · Birkenfeld, DE
Joachim Mahler · Regensburg, DE

Key dates

Filing date	Mar 13, 2013
Grant date	May 26, 2015
Priority date	—
Expiry date	Mar 13, 2033

Classification

Technology area (CPC H)Electricity
CPC primaryH01L2924/3511
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

In various embodiments, a chip arrangement is provided. The chip arrangement may include a chip carrier and a chip mounted on the chip carrier. The chip may include at least two chip contacts and an insulating adhesive between the chip and the chip carrier to adhere the chip to the chip carrier. The at least two chip contacts may be electrically coupled to the chip carrier.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.