Concurrently forming nFET and pFET gate dielectric layers

US9059315B2 · kind B2 · utility

Assignees

• International Business Machines Corporation · US
• GlobalFoundries Inc. · KY

Inventors

• Takashi Ando · Tuckahoe, US
• MaryJane Brodsky · Salt Point, US
• Michael P. Chudzik · Beacon, US
• Min Dai · Hsinchu, TW
• Siddarth A. Krishnan · Newark, US
• Joseph F. Shepard, Jr. · Hopewell Junction, US
• Yanfeng Wang · Qingdao, CN
• Jinping Liu · Ballston Lake, US

Key dates

• Filing date: Jan 2, 2013
• Grant date: Jun 16, 2015
• Expiry date: Sep 22, 2033

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D84/0181

Abstract

Embodiments include methods of forming an nFET-tuned gate dielectric and a pFET-tuned gate dielectric. Methods may include forming a high-k layer above a substrate having a pFET region and an nFET region, forming a first sacrificial layer, a pFET work-function metal layer, and a second sacrificial layer above the first high-k layer in the pFET region, and an nFET work-function metal layer above the first high-k layer in the nFET region and above the second sacrificial layer in the pFET region. The first high-k layer then may be annealed to form an nFET gate dielectric layer in the nFET region and a pFET gate dielectric layer in the pFET region. The first high-k layer may be annealed in the presence of a nitrogen source to cause atoms from the nitrogen source to diffuse into the first high-k layer in the nFET region.