Method of manufacturing scaled equivalent oxide thickness gate stacks in semiconductor devices and related design structure
US9099461B2 · kind B2 · utility
1Cited by
3References
15Claims
0Family size
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Key dates
| Filing date | Jun 7, 2012 |
| Grant date | Aug 4, 2015 |
| Priority date | — |
| Expiry date | Jan 12, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of forming a semiconductor device is disclosed. The method includes: forming a dielectric region on a substrate; annealing the dielectric region in an environment including ammonia (NH3); monitoring a nitrogen peak of at least one of the substrate and the dielectric region during the annealing; and adjusting a parameter of the environment based on the monitoring of the nitrogen peak.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.