Semiconductor structure with reduced junction leakage and method of fabrication thereof
US9105711B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Dec 19, 2013 |
| Grant date | Aug 11, 2015 |
| Priority date | — |
| Expiry date | Dec 19, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/0151
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor structure is formed with a NFET device and a PFET device. The NFET device is formed by masking the PFET device regions of a substrate, forming a screen layer through epitaxial growth and in-situ doping, and forming an undoped channel layer on the screen layer through epitaxial growth. The PFET device is similarly formed by masking the NFET regions of a substrate, forming a screen layer through epitaxial growth and in-situ doping, and forming an undoped channel layer on the screen layer through epitaxial growth. An isolation region is formed between the NFET and the PFET device areas to remove any facets occurring during the separate epitaxial growth phases. By forming the screen layer through in-situ doped epitaxial growth, a reduction in junction leakage is achieved versus forming the screen layer using ion implantation.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.