Sidewall image transfer for heavy metal patterning in integrated circuits
US9171796B1 · kind B1 · utility
5Cited by
5References
19Claims
0Family size
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Key dates
| Filing date | Jun 19, 2014 |
| Grant date | Oct 27, 2015 |
| Priority date | — |
| Expiry date | Jun 19, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method for fabricating a plurality of conductive lines in an integrated circuit includes providing a layer of conductive metal in a multi-layer structure fabricated upon a wafer, forming a spacer in a layer of the multi-layer structure residing above the layer of conductive metal, wherein the spacer is formed from a metal-containing atomic layer deposition material, and transferring a pattern from the spacer to the layer of conductive metal using a sidewall image transfer technique, wherein the transferring results in a formation of the plurality of conductive lines in the layer of conductive material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.