Wafer with intrinsic semiconductor layer
US9177961B2 · kind B2 · utility
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17Claims
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Key dates
| Filing date | Mar 9, 2012 |
| Grant date | Nov 3, 2015 |
| Priority date | — |
| Expiry date | Jan 20, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D87/00
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
The present disclosure relates to a method for the manufacture of a wafer by providing a doped layer on a semiconductor substrate; providing a first semiconductor layer on the doped layer; providing a buried oxide layer on the first semiconductor layer; and providing a second semiconductor layer on the buried oxide layer to form a wafer having a buried oxide layer and a doped layer beneath the buried oxide layer. The disclosure also relates to the wafer that is produced by the new method.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.