Methods for fabricating integrated circuits including fluorine incorporation
US9196475B2 · kind B2 · utility
4Cited by
1References
18Claims
0Family size
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Key dates
| Filing date | Apr 16, 2014 |
| Grant date | Nov 24, 2015 |
| Priority date | — |
| Expiry date | Apr 16, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Integrated circuits and methods for fabricating integrated circuits are provided. In one example, a method for fabricating an integrated circuit includes forming an interlayer of dielectric oxide material in a FET region and overlying a semiconductor substrate. A high-K dielectric layer is deposited overlying the interlayer. Fluorine is incorporated into the interlayer and/or the high-K dielectric layer.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.