FinFETs and techniques for controlling source and drain junction profiles in finFETs

US9202919B1 · kind B1 · utility

Assignees

• STMICROELECTRONICS, INC. · US
• International Business Machines Corporation · US
• GlobalFoundries Inc. · KY

Inventors

• Qing Liu · Guilderland, US
• Ruilong Xie · Niskayuna, US
• Xiuyu Cai · San Diego, US
• Kejia Wang · Fishkill, US
• Chun-Chen Yeh · Clifton Park, US

Key dates

• Filing date: Jul 31, 2014
• Grant date: Dec 1, 2015
• Expiry date: Jul 31, 2034

Classification

• Technology area (CPC H): Electricity
• CPC primary: H10D64/021

Abstract

Techniques and structures for shaping the source and drain junction profiles of a finFET are described. A fin may be partially recessed at the source and drain regions of the finFET. The partially recessed fin may be further recessed laterally and vertically, such that the laterally recessed portion extends under at least a portion of the finFET's gate structure. Source and drain regions of the finFET may be formed by growing a buffer layer on the etched surfaces of the fin and/or growing a source and drain layer at the source and drain regions of the fin. The lateral recess can improve channel-length uniformity along the height of the fin.