Dual gate oxide trench MOSFET with channel stop trench
US9214545B2 · kind B2 · utility
13Cited by
10References
14Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Dec 8, 2014 |
| Grant date | Dec 15, 2015 |
| Priority date | — |
| Expiry date | Dec 8, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/62
Abstract
A semiconductor device has a plurality of gate electrodes over a gate insulator layer formed in active trenches located in an active region of a semiconductor substrate. A first gate runner is formed in the semiconductor substrate and electrically connected to the gate electrodes. The first gate runner abuts and surrounds the active region. A second gate runner is connected to the first gate runner to make contact to a gate metal. A dielectric filled trench surrounds the first and second gate runners and the active region and a highly doped channel stop region is formed under the dielectric filled trench.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.