Method of fabricating electrostatically enhanced fins and stacked nanowire field effect transistors
US9219154B1 · kind B1 · utility
31Cited by
1References
7Claims
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Key dates
| Filing date | Jul 15, 2014 |
| Grant date | Dec 22, 2015 |
| Priority date | — |
| Expiry date | Jul 15, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L21/0262
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Non-planar semiconductor devices including semiconductor fins or stacked semiconductor nanowires that are electrostatically enhanced are provided. The electrostatic enhancement is achieved in the present application by epitaxially growing a semiconductor material protruding portion on exposed sidewalls of alternating semiconductor material portions of at least one hard mask capped semiconductor-containing fin structure that is formed on a substrate.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.