FinFET with insulator under channel
US9224865B2 · kind B2 · utility
11Cited by
6References
9Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Jul 18, 2013 |
| Grant date | Dec 29, 2015 |
| Priority date | — |
| Expiry date | Jul 18, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/017
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A FinFET has a structure including a semiconductor substrate, semiconductor fins and a gate spanning the fins. The fins each have a bottom region coupled to the substrate and a top active region. Between the bottom and top fin regions is a middle stack situated between a vertically elongated source and a vertically elongated drain. The stack includes a top channel region and a dielectric region immediately below the channel region, providing electrical isolation of the channel. The partial isolation structure can be used with both gate first and gate last fabrication processes.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.