Customized alleviation of stresses generated by through-substrate via(S)
US9236301B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Jul 11, 2013 |
| Grant date | Jan 12, 2016 |
| Priority date | — |
| Expiry date | Jul 11, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH01L2924/0002
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Fabrication of through-substrate via (TSV) structures is facilitated by: forming at least one stress buffer within a substrate; forming a through-substrate via contact within the substrate, wherein the through-substrate via structure and the stress buffer(s) are disposed adjacent to or in contact with each other; and where the stress buffer(s) includes a configuration or is disposed at a location relative to the through-substrate via conductor, at least in part, according to whether the TSV structure is an isolated TSV structure, a chained TSV structure, or an arrayed TSV structure, to customize stress alleviation by the stress buffer(s) about the through-substrate via conductor based, at least in part, on the type of TSV structure.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.