Method for creating self-aligned transistor contacts
US9236437B2 · kind B2 · utility
11Cited by
1References
8Claims
0Family size
Assignee
Inventors
Key dates
| Filing date | Feb 20, 2014 |
| Grant date | Jan 12, 2016 |
| Priority date | — |
| Expiry date | Mar 21, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D62/822
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
Embodiments of the present invention provide improved methods of contact formation. A self aligned contact scheme with reduced lithography requirements is disclosed. This reduces the risk of shorts between source/drains and gates, while providing improved circuit density. Cavities are formed adjacent to the gates, and a fill metal is deposited in the cavities to form contact strips. A patterning mask is then used to form smaller contacts by performing a partial metal recess of the contact strips.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.