Methods of forming substantially defect-free, fully-strained silicon-germanium fins for a FinFET semiconductor device
US9245980B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Apr 1, 2014 |
| Grant date | Jan 26, 2016 |
| Priority date | — |
| Expiry date | Jul 31, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D30/751
Abstract
One illustrative method disclosed herein includes, among other things, performing an epitaxial deposition process to form an epi SiGe layer above a recessed layer of insulating material and on an exposed portion of a fin, wherein the concentration of germanium in the layer of epi silicon-germanium (SixGe1-x) is equal to or greater than a target concentration of germanium for the final fin, performing a thermal anneal process in an inert processing environment to cause germanium in the epi SiGe to diffuse into the fin and thereby define an SiGe region in the fin, after performing the thermal anneal process, performing at least one process operation to remove the epi SiGe and, after removing the epi SiGe, forming a gate structure around at least a portion of the SiGe region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.