Semiconductor device including graded gate stack, related method and design structure
US9257519B2 · kind B2 · utility
1Cited by
13References
8Claims
0Family size
Assignee
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Key dates
| Filing date | Nov 15, 2013 |
| Grant date | Feb 9, 2016 |
| Priority date | — |
| Expiry date | Nov 15, 2033 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/693
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A semiconductor device is disclosed. The semiconductor device includes a substrate; and a gate structure disposed directly on the substrate, the gate structure including: a graded region with a varied material concentration profile; and a metal layer disposed on the graded region.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.