Patent · US Active

Extremely thin semiconductor-on-insulator (ETSOI) layer

US9263517B2 · kind B2 · utility

0Cited by

15References

12Claims

0Family size

Assignee

GlobalFoundries Inc. · KY

Inventors

Wagdi W. Abadeer · Jericho, US
Kiran V. Chatty · Williston, US
Jason E. Cummings · Smithfield, US
Toshiharu Furukawa · South Burlington, US
Robert J. Gauthier, Jr. · South Burlington, US
Jed H. Rankin · South Burlington, US
Robert R. Robison · Colchester, US
William R. Tonti · South Burlington, US

Key dates

Filing date	Mar 15, 2013
Grant date	Feb 16, 2016
Priority date	—
Expiry date	Mar 15, 2033

Classification

Technology area (CPC H)Electricity
CPC primaryH10D86/201
WIPO fieldSemiconductors
WIPO sectorElectrical engineering

Abstract

Various aspects include extremely thin semiconductor-on-insulator (ETSOI) layers. In one embodiment, an ETSOI layer includes a plurality of shallow trench isolations (STI) defining a plurality of distinct semiconductor-on-insulator (SOI) regions, the distinct SOI regions having at least three different thicknesses; at least one recess located within the distinct SOI regions; and an oxide cap over the at least one recess.

Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.