Methods of forming a semiconductor device with a protected gate cap layer and the resulting device
US9263537B2 · kind B2 · utility
Assignees
Inventors
Key dates
| Filing date | Oct 28, 2014 |
| Grant date | Feb 16, 2016 |
| Priority date | — |
| Expiry date | Oct 28, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D64/691
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
One method disclosed herein includes forming first and second gate cap protection layers that encapsulate and protect a gate cap layer. A novel transistor device disclosed herein includes a gate structure positioned above a semiconductor substrate, a spacer structure positioned adjacent the gate structure, a layer of insulating material positioned above the substrate and around the spacer structure, a gate cap layer positioned above the gate structure and the spacer structure, and a gate cap protection material that encapsulates the gate cap layer, wherein portions of the gate cap protection material are positioned between the gate cap layer and the gate structure, the spacer structure and the layer of insulating material.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.