Low leakage, low threshold voltage, split-gate flash cell operation
US9275748B2 · kind B2 · utility
Assignee
Inventors
Key dates
| Filing date | Feb 25, 2014 |
| Grant date | Mar 1, 2016 |
| Priority date | — |
| Expiry date | Apr 10, 2034 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10B69/00
- WIPO fieldComputer technology
- WIPO sectorElectrical engineering
Abstract
A method of reading a memory device having rows and columns of memory cells formed on a substrate, where each memory cell includes spaced apart first and second regions with a channel region therebetween, a floating gate disposed over a first portion of the channel region, a select gate disposed over a second portion of the channel region, a control gate disposed over the floating gate, and an erase gate disposed over the first region. The method includes placing a small positive voltage on the unselected source lines, and/or a small negative voltage on the unselected word lines, during the read operation to suppress sub-threshold leakage and thereby improve read performance.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.