Sidewall image transfer process for fin patterning
US9287135B1 · kind B1 · utility
Assignee
Inventors
Key dates
| Filing date | May 26, 2015 |
| Grant date | Mar 15, 2016 |
| Priority date | — |
| Expiry date | May 26, 2035 |
Classification
- Technology area (CPC H)Electricity
- CPC primaryH10D84/853
- WIPO fieldSemiconductors
- WIPO sectorElectrical engineering
Abstract
A method of using sidewall image transfer (SIT) process to pattern fin structures is provided. The method includes providing a fin-patterning substrate containing a first hard-mask layer and a second hard-mask layer over a semiconductor substrate. Trench openings formed on the semiconductor substrate extending vertically through the first hard-mask layer and the second hard-mask layer. Trench openings are filled with a third hard-mask material. The second hard-mask layer is removed to reveal hard-mask mandrels. First sidewall spacers are formed on the opposite sides of the hard-mask mandrels using atomic layer deposition (ALD) process. The semiconductor substrate is etched using the first sidewall spacers and the hard-mask mandrels as mask, subsequently the spacers, the mandrels and the hard-mask layer are removed to reveal fin structures. The method of the present invention is to form fins at a very tight fin pitch by using the very tight thickness controllability of ALD process. By repeating the ALD step twice or more to form multiple SIT spacers the fin pitch size can be reduced further. The inventive method is suitable for fabricating tight fin pitch to less than about 20 nm.
Source: USPTO / EPO open patent data. Objective bibliographic and citation counts.